Views of a Chip 2.1 The Design Hierarchy 2.2 Integrated Circuit Layers 2.3 Photolithography and Patter Transfer 2.4 Planarization 2.5 Electrical Characteristics 2.6 Silicon Characteristics 2.7 Overview of Layout Design 2.8 References 2.9 Exercises Chapter 3. CMOS Technology 3.1 Meet the MOSFETs 3.2 CMOS Fabrication 3.3 Submicron CMOS Processes 3.4 Process Technologies in Microwind 3.5 Masks and Layout 3.6 The Microwind MOS Generator 3.7 Chapter Summary and Roadmap 3.8 References 3.9 Exercises Chapter 4. Using a Layout Editor 4.1 Lambda-Based Layout 4.2 Rectangles and Polygons 4.3 The MOS Generator Revisited 4.4 Summary 4.5 Exercises Chapter 5. CMOS Design Rules 5.1 Types of Rules 5.2 The SCMOS Design Rule Set 5.3 FET Layout 5.4 References 5.5 Exercises Chapter 6.

MOSFETs 6.1 MOSFET Operation 6.2 MOSFET Switch Models 6.3 The Square Law Model 6.4 MOSFET Parasitics 6.5 Comments on Devise Layout 6.6 References 6.7 Exercises Chapter 7. MOSFET Modeling with SPICE 7.1 SPICE Levels 7.2 MOSFET Modeling in Microwind 7.3 Circuit Extraction 7.4 Microwind Level 3 and BSIM4 Equations 7.5 References 7.6 Exercises Chapter 8. CMOS Logic Gates 8.1 The Inverter 8.2 NAND and NOR Gates 8.3 Complex Logic Gates 8.4 The Microwind Compile Command 8.5 Tri-State Circuits 8.6 Large FETs 8.7 Transmission Gates and Pass Logic 8.8 References 8.9 Exercises Chapter 9. Standard Cell Design 9.1 Cell Hierarchies 9.2 Cell Libraries 9.3 Library Entries 9.4 Cell Shapes and Floor Planning 9.5 References 9.6 Exercises Chapter 10.

Storage Elements 10.1 SR Latch 10.2 Bit-level Register 10.3 D-type Flip Flop 10.4 Dynamic DFF 10.5 The Static RAM Cell 10.6 References 10.7 Exercises Chapter 11.

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